Memory devices, especially semiconductor memory devices which store digital data and read that data as necessary for outputting to external devices, have been used in a wide variety of fields and have become indispensable components as advances have been made in recent years in creating digital versions of various types of equipment.
Semiconductor memory devices have increased in capacity, and the level of integration on memory chips has also increased with advances in fine processing technologies in recent years.
The highly integrated semiconductor memory devices mentioned above are designed around memory cells, which are the smallest unit of storage. Unit cells, which are elements that store one of two values (low level or high level), are arrayed in a regular manner in the horizontal (row) direction and the vertical (column) direction on a plane. Thus, they are set in what is referred to as a matrix array.
With this type of memory array, memory cells in the row direction are selected according to the word line. The selection of a word line is carried out by a horizontal decoder (row decoder) after receiving row address input signals from the outside. When a group of memory cells aligned in the column direction is selected according to a word line, the data in the aforementioned memory cells is transferred to a bit line. In addition, each bit line is connected, for example, to a sensing amplifier, used to amplify the signals.
As described above, as memory capacity increases with advances in size reduction technology, the number of memory cells connected to a single bit line increases tremendously. As a result, the sensitivity of the sensing amplifier is adversely affected.
In relation to this, in recent years, highly integrated semiconductor memory devices have been structured to comprise a number of sensing amplifiers, with the memory array divided. Row decoders and sensing amplifiers are thus installed for each subarray unit and are used in storing and reading data.
In addition, with the increase in storage capacity, it has become more difficult to maintain the manufacturing yield for memory chips at a practical level.
For these reasons, one means which has been used to repair defective memory cells, which are a primary cause of the aforementioned decrease in yield, is to equip each subarray in advance with spare memory cells which can be substituted for the defective memory cells in the circuitry. This type of design is referred to as redundant circuitry architecture. The unit which is to be repaired is a memory cell alignment (line) in a single row or a single column along the word line or bit line.
FIG. 9 is a diagram which illustrates the basic concepts behind the redundant circuitry architecture used with conventional highly integrated semiconductor memory devices. In the example shown, the memory array is divided into eight subarrays.
In the figure, SUB0, SUB1, SUB2, SUB3, SUB4, SUB5, SUB6, and SUB7 are subarrays. F.sub.0, F.sub.1, F.sub.2, F.sub.3, F.sub.4, F.sub.5, F.sub.6, and F.sub.7 are repairing circuits installed to correspond to the subarrays SUB0, SUB1, SUB2, SUB3, SUB4, SUB5, SUB6, and SUB7. In addition, WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7 are word lines, and SWL0, SWL1, SWL2, SWL3, SWL4, SWL5, SWL6, and SWL7 are spare word lines. In addition, each of the subarrays SUB0, SUB1, SUB2, SUB3, SUB4, SUB5, SUB6, and SUB7 is provided with a corresponding row decoder RWD0, RWD1, RWD2, RWD3, RWD4, RWD5, RWD6, and RWD7, and sensing amplifier SNS0, SNS1, SNS2, SNS3, SNS4, SNS5, SNS6, and SNS7.
The process of substituting spare word lines for word lines which contain defective memory cells via the repairing circuits F.sub.0, F.sub.1, F.sub.2, F.sub.3, F.sub.4, F.sub.5, F.sub.6, and F.sub.7 is carried out by registering the defective address in the spare decoder, which selects the spare word line. Specific registration means which can be used include electrically blowing the fuse, or blowing the fuse with a laser.
With this type of redundant circuit, if a defective row or memory cell is contained in the memory arrangement in, for example, the subarray SUB0, then that defect is repaired by substituting in the spare word line SWL0 using the repairing circuit F.sub.0.
However, with the above redundant circuit, since repairing circuits and spare word lines are installed for each subarray, creating a one-to-one correspondence between the repairing circuits and the subarrays, it is not possible to use one repairing circuit to repair a defect in a different subarray, which is problematic in that the efficiency of the repairing operation is low.
In addition, when a memory chip is designed such that the memory array is divided into a number of subarrays as described above, the yield will be determined according to the number of spare word lines contained in the subarrays. Thus, with conventional redundant circuit structures, in which word lines are set and repairing circuits are installed for each subarray, as the number of subarrays is increased, the number of spare word lines is also increased, which is problematic in that the yield declines accordingly.
This issue will now be discussed in further detail.
The present case will focus on the dependence of the yield on surface area, assuming that the defect density D of a word line is 20/cm.sup.2.
In this case, the yield for each surface area is calculated based on the Poisson distribution function shown in the formula below. The probability P(n) of the occurrence of a number n of defects in an area A is expressed in the following formula.
(Formula 1) EQU P(n)=(AD).sup.n e.sup.-(AD) /n!
Thus, the probability Q(n), whereby a number n or less of defects may occur, is determined according to the following formula. ##EQU1##
In this case, as shown in FIG. 10, it is assumed that there are 16 repairing circuits contained in the memory cell area A. The following are examples of correspondence between the repairing circuits and the memory cell area A.
a: 16 repairing circuits in A as a whole PA1 b: 8 repairing circuits.times.2 in (1/2) A PA1 c: 4 repairing circuits.times.4 in (1/4) A PA1 d: 2 repairing circuits.times.8 in (1/8) A PA1 e: 1 repairing circuits.times.16 in (1/16) A
Based on the above hypotheses, it is possible to calculate the yield for the memory cell area A in the corresponding examples (a-e), based on the Poisson distribution function. The probability P(n), whereby a number n of defects may occur in the area A, is expressed according to Formula (1) described above.
Thus, the yield Pa in the memory cell area A for the example in (a) can be expressed as shown in Formula (3) based on the aforementioned Formula (2), since it indicates the probability that 16 or less defects will occur in A. ##EQU2##
In addition, the yield Pb for the memory cell area A in the example in b is expressed by the following formula. ##EQU3##
In addition, the yields Pc, Pd, and Pe in the memory cell area A for the examples in c-e can be respectively expressed by the following formulas. ##EQU4##
FIG. 11 is a graph which illustrates yield with respect to defect density in each of the examples a-e described above. Defect density is presented on the horizontal axis, and yield is presented on the vertical axis.
As FIG. 11 makes clear, it is possible to obtain a higher yield by relating the repairing circuits to the area as a whole, than by relating them to e divided area.
Thus, with redundant structures such as that shown in FIG. 9, yield is determined according to the number of spare word lines contained in each subarray.
FIG. 12 is a graph which illustrates the calculation results for a case in which 1-Q(n) is taken as row yield. In the figure, the number of spare (redundant) word lines is shown on the horizontal axis, and the yield is shown on the vertical axis.
In addition, the corresponding surface areas are as shown in Table I below.
TABLE I ______________________________________ Blocks Area ______________________________________ Block A (1 subarray) 0.0105 cm.sup.2 Block 8 (8 subarrays) 0.084 cm.sup.2 Block 16 (16 subarrays) 0.168 cm.sup.2 Block 32 (32 subarrays) 0.336 cm.sup.2 Block 128 (128 subarrays) 1.344 cm.sup.2 ______________________________________
It should be noted that in the graph shown in FIG. 12, a borderline is drawn at 90%. The numerals shown on the top of each curve denote the number of spare word lines, corresponding to the given area, which are required for yield to exceed 90% when the defect density D=20/cm.sup.2.
The numbers of spare word lines shown in FIG. 12 which are required for yield to exceed 90% when defect density D=20/cm.sup.2 are as shown below in Table II.
TABLE II ______________________________________ Required number of Actual number of Blocks spare word lines spare word lines ______________________________________ Block A (1 time) 1 1 Block 8 (8 times) 3 8 Block 16 (16 times) 6 16 Block 32 (32 times) 10 32 Block 128 (128 times) 34 128 ______________________________________
As FIG. 12 and Table II make clear, an increase in the number of blocks, i.e., an increase in the number of subarrays, causes an increase in the value of (required number of spare word lines)/(actual number of spare word lines). Thus, the number of unnecessary spare word lines increases.
Specifically, in memory chips divided into a number of subarrays, as shown in FIG. 9, redundant circuits, which comprise. repairing circuits and spare word lines for each subarray such that the repairing circuits and subarrays have a one-to-one correspondence, cause the memory chip yield to be determined according to the number of spare word lines contained in the subarray.
Thus, the conventional redundant architecture shown in FIG. 9 results in poor efficiency in the repairing operation.
The present invention has been developed in light of the above conditions, and has the objective of providing a semiconductor memory device which is very efficient in repairing defects, thus making it possible to improve yield.